Technical Field
This disclosure relates to improving integrated circuit (IC) manufacturing yield. More specifically, this disclosure relates to identifying a failure mechanism based on a population of scan diagnostic reports.
Related Art
Advances in process technology and a practically unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of IC designs. Manufactured ICs go through rigorous testing, and the percentage (or fraction) of manufactured ICs that pass testing is called the yield. When a new manufacturing process is introduced or a new IC is manufactured using an existing manufacturing process, the yield can be significantly lower than what is considered to be economically acceptable. Therefore, improving the yield of manufactured ICs to an acceptable level is very important for meeting time-to-market and time-to-volume objectives for the IC.
If we can identify the reason why manufactured ICs are failing a given set of tests, then this information can be used to increase the yield by making appropriate adjustments to the manufacturing process and/or to the circuit design. Scan diagnosis uses the circuit design information, Automatic Test Pattern Generation (ATPG) patterns, and the pass/fail results from the tests to identify specific locations in the circuit design that may contain defects. Unfortunately, the output of scan diagnosis is ambiguous and it is difficult, if not impossible, to directly use the scan diagnosis output to improve the yield. The ambiguity in the output of the scan diagnosis is referred to as diagnostic noise, and the reasons for the diagnostic noise are twofold. First, more than one location in the circuit design can explain why a manufactured IC failed a particular test. Therefore, the scan diagnosis output provides a set of possible locations that may have caused a particular test to fail, but does not identify which of the possible locations is the actual reason for the test failure. Second, in each possible location identified by the scan diagnosis there could be many possible defects, and any one of those defects may have resulted in the test failure. For example, scan diagnosis may identify a chain of inverters as the reason for test failure, but any one of a large number of defects in the chain of inverters (e.g., specific cells, vias, wires, etc. within the chain of inverters) could have caused the test to fail.
In a publication entitled “Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnostic Results,” by Brady Benware, Chris Schuermyer, Manish Sharma, and Thomas Herrmann, IEEE Design & Test of Computers, p. 8-18, February 2012, the authors describe an approach for identifying the root causes for test failures (this approach is also described in U.S. Pub. No. 2012/0297264). The approach uses a Bayes Net Mixture Model to represent the features and uses a frequentist approach (specifically expectation maximization) to learn the parameters of the model. The Bayes Net Mixture Model restricts the topic assignments to only be a mixture of the original set of features. For example, a real silicon defect may be due to a specific type and orientation of a via routed around certain type of standard cell. If the input features are {cells, vias}, then the above-mentioned mixture model will force assignment into exactly one feature, e.g., a particular cell, a particular via, etc. Some other approaches use supervised machine learning or clustering with hard assignments to try to remove diagnostic noise.
Common approaches for removing diagnostic noise are often focused on identifying only a single type of defect at a time, and can incorrectly identify the root cause. Therefore, what are needed are techniques and systems to remove diagnostic noise more effectively, thereby enabling the yield of manufactured ICs to be quickly increased to an acceptable level.